1. Field of the Invention
The present invention relates to semiconductor devices and fabrication methods therefor. More particularly, the invention pertains to methods for forming conductive blind vias (blind wafer interconnects) in a substrate such as a semiconductor wafer or other substrate, and related structures and assemblies.
2. Background of Related Art
Semiconductor devices that have integrated circuits are produced by fabricating a large plurality of identical circuit patterns on a semiconductor wafer or other bulk semiconductor substrate. Each circuit pattern defines the location of a semiconductor die, there being circuit-devoid areas, commonly termed “streets” between each semiconductor die location. A plethora of processes is typically used, including, for example, deposition, plating, doping, photolithography, etching, laser ablation, oxidation, nitridation, mechanical and chemical-mechanical planarization, wafer thinning, die separation (singulation), testing and packaging. Inasmuch as major goals of semiconductor manufacturers are increased performance and lower cost, considerations such as device density (with concomitant circuit speed and reduced power requirements) and enhanced reliability have taken a high priority. The proliferation of hand-held apparatus such as cellular phones, GPS units, entertainment devices, PDAs, and the like has incentivized development of electronic circuitry of greatly reduced size and enhanced capabilities in terms of function and speed. In addition, a significant manufacturing goal to enhance throughput, reduce cost and minimize handling of semiconductor dice after singulation is to perform as many of the fabrication, test and packaging processes on an entire wafer prior to die separation (singulation).
One of the critical limitations in the production of miniature semiconductor devices relates to electrical conductors for connection of their integrated circuit(s) to an apparatus such as a circuit board or another die. Conventionally, a semiconductor device has an array of conductive bond pads electrically connected to the integrated circuit (IC) by active surface metallization. Connection of these bond pads to another device or circuit board may conventionally utilize fine wires, commonly termed wire bonds, which are subject to displacement (leading to short-circuits with other conductors) and breakage (leading to open circuits). Despite having a relatively long history of widespread use in the industry, wire-bonding remains a time-consuming and expensive process. The propensity to wire damage is increased as the devices become more miniaturized and dense. Where a plurality of individual dice are joined to form a multi-chip module (MCM), wiring costs and high rates of wire damage represent particularly substantial problems. Further, wire bonds exhibit undesirably high inductance, 5 nH being typical.
One way to increase the density of semiconductor devices in a semiconductor assembly is to stack semiconductor dice one upon another. The semiconductor dice may be interconnected by forming conductive vias passing through the semiconductor substrate material, perpendicular to the active surface. The vias are filled with an electrically conductive material and the vias are connected, either directly or through metallization, to integrated circuitry fabricated on active surfaces of a semiconductor wafer. Thus, the vias provide a conductive pathway from the active surface of a semiconductor die to its back surface, enabling interconnection of via ends on the back surface of the semiconductor die to external electrical contacts of another semiconductor die or a carrier substrate, such as a circuit board, interposer or other higher level packaging. Via holes may be conventionally formed by mechanical drilling, etching, laser ablation, or a combination thereof. In an etching method, photolithographic processing of a photoresist may be used to define a pattern and size for the via holes, followed by wet (chemical) or dry (reactive ion) etching of unmasked areas of the substrate. Laser ablation has been used to form vias by ablating semiconductor material from a semiconductor substrate to form holes extending through a partial thickness or the entire thickness of the substrate. Substrate material damaged by the heat of the laser is then often removed by a subsequent wet etch process.
Various conductive structures on a semiconductor die or wafer may be interconnected or connected to other components by a via, including bond pads, component leads, metal wires, metal layers and annular rings. Bond pads on semiconductor dice are typically formed from tungsten, aluminum, copper, or aluminum-copper alloys having less than about 0.5% copper, although other materials may be used.
A conductive via passing between a wafer back side and the underside of a conductive structure on or in the active surface of the wafer may be defined herein as a blind wafer interconnect (BWI). Such a via has theoretical advantages including the following: (a) conductor lengths are shortened, enhancing circuit speed; (b) the die footprint is not increased by die interposers, bond wires, TAB connectors, etc.; and (c) a die may be electrically connected to carrier substrates, semiconductor dice and other components from both its active surface and its back side.
In a conventional method, BWIs are formed by the acts of etching or laser-ablating holes, or both, through a semiconductor substrate (e.g., wafer or die) from the back side, blanket-depositing or forming a layer of passivating material on the back side of the semiconductor substrate and on the walls of the holes, lining or filling the holes with a conductive material such as solder and thinning the substrate back side by an abrasive technique such as chemical mechanical planarization (CMP) to a desired substrate thickness. The CMP results in a bare semiconductor (e.g., silicon) surface which closely abuts the conductive via, leading to potential short-circuiting to the substrate material when a solder ball or other conductor is joined to the conductive via end.
In order to prevent short-circuiting, the bare semiconductor substrate back side (excluding via ends) may be selectively etched back so that the via end with surrounding passivating layer may protrude from the etched back, substrate back side. Then, a further layer of passivating material may be blanket-deposited over the substrate back side to ensure complete dielectric coverage about the via end. However, the face of the protruding via end will also become covered with passivating material, which must be removed before the via end can be conductively joined to a solder ball, solder column or other external connector. Such passivating material removal may be accomplished by a mask-and-etch technique requiring additional process acts. Overall, this method requires numerous acts, is costly, and may not achieve the desired reliability.
A method for improving the connection of hollow through hole vias in a printed circuit board (PCB) to an electronic module is described in U.S. Pat. No. 5,275,330 to Isaacs et al. As shown in this reference, each via is filled step-wise until completely filled, prior to placement and attachment of solder balls of a module. Multiple pass solder plugging steps are required and assembly yield is lower than desirable. This method may sometimes result in other problems, including molten/softened solder drainage from the via due to gravity and replacement by solder from the adjacent solder ball.
As shown in U.S. Pat. No. 6,076,726 to Hoffmeyer et al., it is proposed to plate cylindrical via walls with a metal, such as nickel, which is not wetted sufficiently by the reflowing of a lead-tin eutectic solder using fluxes which allow good wetting to copper. A capture pad of the via is copper plated to effect good wetting to a solder ball. The goal of the reference is to form a hollow (cylindrical) via which is not wettable for solder adhesion, while the capture pad is wetted.
There are substantial differences in forming vias in a circuit board and forming vias in a semiconductor wafer bearing many discrete microchip circuits. While a circuit board is typically manufactured at a desired final thickness, semiconductive materials such as silicon and the like are fragile materials, subject to easy fracture. Fabrication of electronic devices on an entire semiconductor wafer is typically conducted before the wafer is thinned by a back grinding process such as CMP to a desired final thickness. Thus, for example, in conventional practice, multiple circuits may be formed on a wafer having an initial thickness of about 725 μm to 750 μm, and the wafer is then back-ground to a desired thickness of between about 150 μm and 250 μm. Any further processing in wafer form is then followed by semiconductor die singulation and packaging.
Efforts to overcome the disadvantages of the prior art with respect to the use of vias in a semiconductor substrate have led the inventors herein to the methods of the present invention.